1. Field of the Invention
The present invention relates to a wiring substrate having a build-up layer superposed on one side of a core substrate.
2. Description of the Related Art
FIG. 7 shows a cross section of a main portion of a wiring substrate 40 including a core substrate 41, a build-up layer BU1 formed on a front surface 42 of the core substrate 41, and a build-up layer BU2 formed on a back surface 43 of the core substrate 41. The core substrate 41 is formed of a glass-epoxy resin and has a relatively small thickness of 0.2–0.4 mm. A plurality of through holes 44 are formed in the core substrate 41 so as to extend between the front surface 42 and the back surface 43. Each of the through holes 44 has a through hole conductor 45 formed therein and is filled with a filter resin 46.
As shown in FIG. 7, a predetermined pattern of a wiring layer 48 is formed on the front surface 42 of the core substrate 41 and is connected to the upper ends of the through hole conductors 45. A dielectric layer 50 formed of an epoxy resin is formed on the front surface 42 and on the wiring layer 48, and filled via conductors 52 are formed in the dielectric layer 50 at predetermined positions located on the wiring layer 48.
As shown in FIG. 7, a dielectric layer 56 and a wiring layer 54 are formed on the dielectric layer 50, and the wiring layer 54 is connected to the upper ends of the via conductors 52. Filled vias 58 are formed in the dielectric layer 56 at predetermined positions located on the wiring layer 54. A solder resist layer (a dielectric layer) 60 and a wiring layer 62 are formed on the dielectric layer 56, and the wiring layer 62 is connected to the upper ends of the via conductors 58. The wiring layers 48, 54, and 62 and the dielectric layers 50, 56, and 60 constitute the build-up layer BU1.
As shown in FIG. 7, a plurality of solder bumps 66 are separately formed on the wiring layer 62 at predetermined positions so as to project upward from a first main surface 64, which is the surface of the solder resist layer 60. The bumps 66 are connected to corresponding connection terminals 70 formed on the bottom surface of an IC chip (a semiconductor device) 68 to be mounted on the first main surface 64.
A copper reinforcement (stiffener) 72, which is a frame having a substantially rectangular shape as viewed from above, is bonded onto the first main surface 64 by use of an unillustrated adhesive so as to surround the IC chip 68.
As shown in FIG. 7, a wiring layer 47 is formed on the back surface 43 of the core substrate 41 and is connected to the lower ends of the through hole conductors 45. As in the case of the build-up layer BU1, a build-up layer BU2 is formed on the wiring layer 47, build-up layer BU2 including dielectric layers 49 and 55, a solder resist layer (a dielectric layer) 63, wiring layers 53 and 59, and filled via conductors 51 and 57. A plurality of solder bumps 67 are separately formed on the wiring layer 59 at predetermined positions so as to project downward from a second main surface 65. The bumps 67 are connected to corresponding connection terminals 71 formed on chip capacitors (electronic components) 69 to be mounted on the second main surface 65.
3. Problems to be Solved by the Invention
However, in the above-described wiring substrate 40 configured such that the build-up layers BU1 and BU2 are formed on the corresponding opposite sides of the core substrate 41, the IC chip 68 is electrically connected to the chip capacitors 69 via the wiring layers 62, 54, and 48, the through hole conductors 45, the wiring layers 47, 58, 59, etc. As a result, the electrically continuous path becomes long, resulting in instability of electrical characteristics, such as an increase in loop inductance.
In order to cope with the above problem, the distance between the IC chip 68 and the chip capacitor 69 can be reduced in the following manner: the thickness of the core substrate 41 is reduced to 0.4 mm or less, and only the build-up layer BU1 on the front surface 42 is formed. However, in this case, the strength of the overall wiring substrate 40 is reduced, resulting in deflection or warpage. In order to prevent such deflection or warpage, the metallic reinforcement 72 must be disposed on the first main surface 64, resulting in increased cost.